1. Field of the Invention
The present invention relates to a master-slave flip-flop circuit and, more particularly, to a flip-flop circuit used in a sequential logic circuit such as a shift register or a counter.
2. Description of the Related Art
Heretofore, when the level of an input signal is inverted in a flip-flop circuit or a sequential logic circuit containing a flip-flop circuit, the level of the output signal is once inverted and again inverted to its original state. This phenomenon is sometimes called a hazard of the output signal. It causes an erroneous operation in an applied circuit in which the output signal is input to a circuit in the applied circuit as a clock signal. In a conventional master-slave flip-flop circuit shown in FIG. 1 the hazard occurs by an anticoincidence of the circuit threshold value V.sub.thCH of a holding circuit 3 for holding the output signal of a master stage circuit 1 with the threshold value circuit V.sub.thCS of the input circuit of a slave stage circuit 2. Heretofore, in order to make V.sub.thCH coincide with V.sub.thCS as much as possible, the size of the transistors (not shown) of the clocked inverter of the holding circuit 3 is equalized to the size of the transistors of the clocked inverter 5 of the slave stage circuit 2 (FIG. 2). Alternatively, the circuit threshold value of the inverter 6 of the holding circuit 3 is matched to that of the clocked inverter 5 of the input circuit of the slave stage circuit 2 (FIG. 3).
A process through which the above-mentioned output hazard is generated in the master-slave flip-flop circuit of prior art when the circuit threshold value of the master output holding circuit is unbalanced from that of the input circuit of the stave stage circuit will be described. FIG. 4A shows the same master-slave flip-flop circuit as that in FIG. 3, and FIG. 4B shows a clock signal generator for generating a clock signal to be input to the circuit in FIG. 4A. (i) In the flip-flop circuit shown in FIG. 4A, assume that the circuit threshold value V.sub.thCS of the clocked inverter 5 of the slave stage circuit 2 is higher than the circuit threshold value V.sub.thCH of the inverter 6 of the holding circuit 3. When the data input D of a flip-flop circuit is changed from a high level (hereinafter referred to as "H") to a low level (hereinafter referred to as "L") and a clock input CK is altered from "L" to "H", an output Q is changed from "H" to "L" if data is sufficiently early varied with respect to a clock input as shown in FIG. 5. On the other hand, if the data input D is altered in delay with respect to the change of the clock input CK as shown in FIG. 6, the output Q remains "H", and the level of the output Q is not varied. If the changes of the data input D and the clock input CK is very close as shown in FIG. 9, the potential of a point A shown in FIG. 4A is gradually altered from "H" to "L" to reach the circuit threshold value V.sub.thCS of the clocked inverter 5 of the slave stage circuit 2. Then, the output Q of the slave stage circuit 2 is inverted, and varied from "H" to "L". However, since the potential of the point A does not reach the circuit threshold value V.sub.thCH of the holding circuit, the potential of a point B remains "L" and does not change. Therefore, when the clock input is altered from "L" to "H", the level of the point A is raised to an "H" level by the clocked inverter 8.
When the potential of the point A is gradually raised to reach the V.sub.thCS, the output Q of the slave stage circuit 2 is again inverted to change from "L" to "H". (ii) Assume that the circuit threshold value of the clocked inverter 4 is lower than that of the inverter 6. When the data input D of the flip-flop circuit is changed from a level "L" to a level "H" and the clock input CK is altered from "L" to "H", the output D is changed from "L" to "H" if the data input D is varied sufficiently early with respect to the change of the clock input CK as shown in FIG. 7. On the other hand, the output remains "L" and the level of the output is not varied if the data input D is changed in delay with respect to the change of the clock input CK as shown in FIG. 8. If the change of the data input D and the clock input CK are very close as shown in FIG. 10, the potential of the point A shown in FIG. 4A is gradually changed from "L" to "H" to reach the threshold value V.sub.thCS of the slave stage circuit 2. Then, the output Q of the slave stage circuit 2 is inverted to alter from "L" to "H". However, since the potential of the point A does not reach the circuit threshold value V.sub.thCH of the holding circuit 3, the potential of the point B remains "H" and does not change. Therefore, when the clock input is altered from "L" to "H", the level of the point A is lowered to a "L" level by the clocked inverter 8.
When the potential of the point A is gradually lowered to reach the V.sub.thCS, the output Q of the slave stage circuit is again inverted to alter from "H" to "L".
The hazard of the output signal occurs under the conditions as shown in the above paragraphs (i) and (ii).
Since the strict matching of the circuit threshold value of the holding circuit 3 to that of the input circuit of the slave stage circuit 2 is impossible in a actual manufacturing environment, the above-mentioned hazard occurs if two or more control signals for specifying the operation of the flip-flop circuit in FIG. 4A are simultaneously changed.
Even when the transistor cell sizes of the holding circuit 3 and the slave stage circuit 2 are equally designed in the circuit, as shown, for example, in FIG. 2, there is not always a guarantee of matching the circuit threshold values of both the circuits due to irregularities in process parameters. In the circuit arrangement shown in FIG. 3, it is impossible to always match the circuit threshold value of the clocked inverter 5 of the slave stage circuit 2 when the clock input is changed to that of the inverter 6 of the holding circuit 3.